A continuing goal of the semiconductor industry has been to increase the memory density (e.g., the number of memory cells per memory die) of memory devices, such as non-volatile memory devices (e.g., NAND Flash memory devices). One way of increasing memory density in non-volatile memory devices is to utilize a vertical memory array (also referred to as a “three-dimensional (3D) memory array”) architecture. A conventional vertical memory array includes semiconductor pillars extending through openings in tiers of conductive structures (e.g., control gates, access lines, etc.) and dielectric materials at each junction of the semiconductor pillars and the conductive structures. Such a configuration permits a greater number of transistors to be located in a unit of die surface area by building the array upwards (e.g., vertically) on a die, as compared to structures with conventional planar (e.g., two-dimensional) arrangements of transistors.
Conventional vertical memory arrays include tiers of conductive structures (e.g., access lines, word lines, etc.) separated by dielectric material. Some conventional vertical memory arrays require capacitors for operably coupling one or more components of the vertical memory array to one another, such as to reduce noise between two buses (e.g., between a power bus and a ground bus). Forming capacitors in such memory arrays requires additional real estate on the semiconductor device. In some embodiments, capacitors may be formed by directly contacting conductive word line materials to form an electrical contact, such as by forming electrical contacts to individual levels of the word line materials with a so-called “stair-step” structure. However, the stair-step structures may consume a significant amount of real estate, often larger than that available for the capacitor. In some instances, due to the real estate required to electrically contact the word lines, only a portion of the available word line levels are contacted for a capacitor structure.
In addition to requirements to increase memory density and reduce the size of memory arrays, it is a goal to reduce the footprint of other portions of semiconductor devices, such as at peripheral regions of semiconductor devices. By way of nonlimiting example, it is a goal to reduce the size of portions of a semiconductor die peripheral to a memory array, such as portions that may be coupled to sub-array features, power buses, ground buses, charge pumps, a power side decoupling capacitor, etc.